mental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity breakthrough. In the second edition of Writing Testbenches, Bergeron raises the verification level of abstraction by introducing coverage-driven constrained-random transaction-level self-checking testbenches all made possible through the introduction of hardware verification languages (HVLs), such as e from Verisity and OpenVera from Synopsys. The state-of-art methodologies described in Writing Test benches will contribute greatly to the much-needed equivalent of a synthesis breakthrough in verification productivity. I not only highly recommend this book, but also I think it should be required reading by anyone involved in design and verification of today's ASIC, SoCs and systems. Harry Foster Chief Architect Verplex Systems, Inc. xviii Writing Testbenches: Functional Verification of HDL Models PREFACE If you survey hardware design groups, you will learn that between 60% and 80% of their effort is now dedicated to verification.
Verification is too often approached in an ad hoc fashion. Visually inspecting simulation results is no longer feasible and the directed test-case methodology is reaching its limit. Moore's Law demands a productivity revolution in functional verification methodology. Writing Testbenches Using SystemVerilog offers a clear blueprint of a verification process that aims for first-time success using the SystemVerilog language. From simulators to source management tools, from specification to functional coverage, from I's and O's to high-level abstractions, from interfaces to bus-functional models, from transactions to self-checking testbenches, from directed testcases to constrained random generators, from behavioral models to regression suites, this book covers it all. Writing Testbenches Using SystemVerilog presents many of the functional verification features that were added to the Verilog language as part of SystemVerilog. Interfaces, virtual modports, classes, program blocks, clocking blocks and others SystemVerilog features are introduced within a coherent verification methodology and usage model. Writing Testbenches Using SystemVerilog introduces the reader to all elements of a modern, scalable verification methodology. It is an introduction and prelude to the verification methodology detailed in the Verification Methodology Manual for SystemVerilog. It is a SystemVerilog version of the author's bestselling book Writing Testbenches: Functional Verification of HDL Models.
CHAPTER 6 Architecting Testbenches 221 Reusable Verification Components 221 Procedural Interface 225 Development Process 226 Verilog Implementation 227 Packaging Bus-Functional Models 228 Utility Packages 231 VHDL Implementation 237 Packaging Bus-Functional Procedures 238 240 Creating a Test Harness 243 Abstracting the Client/Server Protocol Managing Control Signals 246 Multiple Server Instances 247 Utility Packages 249 Autonomous Generation and Monitoring 250 Autonomous Stimulus 250 Random Stimulus 253 Injecting Errors 255 Autonomous Monitoring 255 258 Autonomous Error Detection Input and Output Paths 258 Programmable Testbenches 259 Configuration Files 260 Concurrent Simulations 261 Compile-Time Configuration 262 Verifying Configurable Designs 263 Configurable Testbenches 265 Top Level Generics and Parameters 266 Summary 268 CHAPTER 7 Simulation Management 269 Behavioral Models 269 Behavioral versus Synthesizable Models 270 Example of Behavioral Modeling 271 Characteristics of a Behavioral Model 273 x Writing Testbenches: Functional Verification of HDL Models Modeling Reset 276 Writing Good Behavioral Models 281 Behavioral Models Are Faster 285 The Cost of Behavioral Models 286 The Benefits of Behavioral Models 286 Demonstrating Equivalence 289 Pass or Fail? 289 Managing Simulations 292 294 Configuration Management Verilog Configuration Management 295 VHDL Configuration Management 301 SDF Back-Annotation 305 Output File Management 309 Regression 312 Running Regressions 313 Regression Management 314 Summary 316 APPENDIX A Coding Guidelines 317 Directory Structure 318 VHDL Specific 320 Verilog Specific 320 General Coding Guidelines 321 Comments 321 Layout 323 Syntax 326 Debugging 329 Naming Guidelines 329 Capitalization 330 Identifiers 332 Constants 334 334 HDL Specific Filenames 336 HDL Coding Guidelines 336 337 Structure 337 Layout
The Definitive, Up-to-Date Guide to Digital Design with SystemVerilog: Concepts, Techniques, and Code To design state-of-the-art digital hardware, engineers first specify functionality in a high-level Hardware Description Language (HDL)—and today’s most powerful, useful HDL is SystemVerilog, now an IEEE standard. Digital System Design with SystemVerilog is the first comprehensive introduction to both SystemVerilog and the contemporary digital hardware design techniques used with it. Building on the proven approach of his bestselling Digital System Design with VHDL, Mark Zwolinski covers everything engineers need to know to automate the entire design process with SystemVerilog—from modeling through functional simulation, synthesis, timing simulation, and verification. Zwolinski teaches through about a hundred and fifty practical examples, each with carefully detailed syntax and enough in-depth information to enable rapid hardware design and verification. All examples are available for download from the book's companion Web site, zwolinski.org. Coverage includes Using electronic design automation tools with programmable logic and ASIC technologies Essential principles of Boolean algebra and combinational logic design, with discussions of timing and hazards Core modeling techniques: combinational building blocks, buffers, decoders, encoders, multiplexers, adders, and parity checkers Sequential building blocks: latches, flip- flops, registers, counters, memory, and sequential multipliers Designing finite state machines: from ASM chart to D flip-flops, next state, and output logic Modeling interfaces and packages with SystemVerilog Designing testbenches: architecture, constrained random test generation, and assertion-based verification Describing RTL and FPGA synthesis models Understanding and implementing Design-for-Test Exploring anomalous behavior in asynchronous sequential circuits Performing Verilog-AMS and mixed-signal modeling Whatever your experience with digital design, older versions of Verilog, or VHDL, this book will help you discover SystemVerilog’s full power and use it to the fullest.
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today’s digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.
Digital Electronics and Design with VHDL offers a friendly presentation of the fundamental principles and practices of modern digital design. Unlike any other book in this field, transistor-level implementations are also included, which allow the readers to gain a solid understanding of a circuit's real potential and limitations, and to develop a realistic perspective on the practical design of actual integrated circuits. Coverage includes the largest selection available of digital circuits in all categories (combinational, sequential, logical, or arithmetic); and detailed digital design techniques, with a thorough discussion on state-machine modeling for the analysis and design of complex sequential systems. Key technologies used in modern circuits are also described, including Bipolar, MOS, ROM/RAM, and CPLD/FPGA chips, as well as codes and techniques used in data storage and transmission. Designs are illustrated by means of complete, realistic applications using VHDL, where the complete code, comments, and simulation results are included. This text is ideal for courses in Digital Design, Digital Logic, Digital Electronics, VLSI, and VHDL; and industry practitioners in digital electronics. Comprehensive coverage of fundamental digital concepts and principles, as well as complete, realistic, industry-standard designs Many circuits shown with internal details at the transistor-level, as in real integrated circuits Actual technologies used in state-of-the-art digital circuits presented in conjunction with fundamental concepts and principles Six chapters dedicated to VHDL-based techniques, with all VHDL-based designs synthesized onto CPLD/FPGA chips
The International Conference on Signals, Systems and Automation (ICSSA 2011) aims to spread awareness in the research and academic community regarding cutting-edge technological advancements revolutionizing the world. The main emphasis of this conference is on dissemination of information, experience, and research results on the current topics of interest through in-depth discussions and participation of researchers from all over the world. The objective is to provide a platform to scientists, research scholars, and industrialists for interacting and exchanging ideas in a number of research areas. This will facilitate communication among researchers in different fields of Electronics and Communication Engineering. The International Conference on Intelligent System and Data Processing (ICISD 2011) is organized to address various issues that will foster the creation of intelligent solutions in the future. The primary goal of the conference is to bring together worldwide leading researchers, developers, practitioners, and educators interested in advancing the state of the art in computational intelligence and data processing for exchanging knowledge that encompasses a broad range of disciplines among various distinct communities. Another goal is to promote scientific information interchange between researchers, developers, engineers, students, and practitioners working in India and abroad.
Suitable for use in a one- or two-semester course for computer and electrical engineering majors. VHDL for Engineers, First Edition is perfect for anyone with a basic understanding of logic design and a minimal background in programming who desires to learn how to design digital systems using VHDL. No prior experience with VHDL is required. This text teaches readers how to design and simulate digital systems using the hardware description language, VHDL. These systems are designed for implementation using programmable logic devices (PLDs) such as complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). The book focuses on writing VHDL design descriptions and VHDL testbenches. The steps in VHDL/PLD design methodology are also a key focus. Short presents the complex VHDL language in a logical manner, introducing concepts in an order that allows the readers to begin producing synthesizable designs as soon as possible.
For the new millenium, Wai-Kai Chen introduced a monumental reference for the design, analysis, and prediction of VLSI circuits: The VLSI Handbook. Still a valuable tool for dealing with the most dynamic field in engineering, this second edition includes 13 sections comprising nearly 100 chapters focused on the key concepts, models, and equations. Written by a stellar international panel of expert contributors, this handbook is a reliable, comprehensive resource for real answers to practical problems. It emphasizes fundamental theory underlying professional applications and also reflects key areas of industrial and research focus. WHAT'S IN THE SECOND EDITION? Sections on... Low-power electronics and design VLSI signal processing Chapters on... CMOS fabrication Content-addressable memory Compound semiconductor RF circuits High-speed circuit design principles SiGe HBT technology Bipolar junction transistor amplifiers Performance modeling and analysis using SystemC Design languages, expanded from two chapters to twelve Testing of digital systems Structured for convenient navigation and loaded with practical solutions, The VLSI Handbook, Second Edition remains the first choice for answers to the problems and challenges faced daily in engineering practice.
This rigorous text shows electronics designers and students how to deploy Verilog in sophisticated digital systems design.The Second Edition is completely updated -- along with the many worked examples -- for Verilog 2001, new synthesis standards and coverage of the new OVI verification library.
FPGA Prototyping Using Verilog Examples will provide you with a hands-on introduction to Verilog synthesis and FPGA programming through a “learn by doing” approach. By following the clear, easy-to-understand templates for code development and the numerous practical examples, you can quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify the operation of its physical implementation. This introductory text that will provide you with a solid foundation, instill confidence with rigorous examples for complex systems and prepare you for future development tasks.
This book provides step-by-step guidance on how to design VLSI systems using Verilog. It shows the way to design systems that are device, vendor and technology independent. Coverage presents new material and theory as well as synthesis of recent work with complete Project Designs using industry standard CAD tools and FPGA boards. The reader is taken step by step through different designs, from implementing a single digital gate to a massive design consuming well over 100,000 gates. All the design codes developed in this book are Register Transfer Level (RTL) compliant and can be readily used or amended to suit new projects.
Covers the methodology and state-of-the-art techniques of constrained verification, which is new and popular. It relates constrained verification with the also-hot technology called assertion-based design. Discussed and clarifies language issues, critical to both the above, which will help the implementation of these languages.
VHDL Modeling and Design Flow VLSI : Complete VLSI design flow (with reference to an EDA tool), Sequential, Data flow and structural modeling, Functions, Procedures, Attributes, Test benches, Synthesizable and non-synthesizable statements; Packages and configurations modeling in VHDL with examples of circuits such as counters, Shift registers, Bidirectional bus, etc. FSM and Sequential Logic Principles Sequential circuits, Meta-stability synchronization, Design of finite state machines and state minimization, FSM CASE STUDIES - Traffic light control, Lift control and UART, STA and DTA. Programmable Logic Devices The CPLDs, Study of architecture of CPLD and study of the architecture of FPGA.System On Chip One, Two phase clock, Clock distribution, Power distribution, Power optimization, SRC and DRC, Design validation, Global routing, Switch box routing, Off chip connections, I/O architectures, Wire parasitics, EMI immune design, Study of memory-Basics of memory includes types of memory cells and memory architectures, Types of memory based on architecture specific and application specific viz. SRAM, DRAM, SDRAM, FLASH, FIFO. CMOS VLSI CMOS parasitics, Equivalent circuit, Body effect, Technology scaling, parameter, Detail study of inverter characteristics, Power dissipation, Power delay product, CMOS combinational logic design and W/L calculations, Transmission gates, Introduction to CMOS layout. Testability Need of design for testability, Introduction to fault coverage, Testability, Design-for-Testability, Controllability and Observability, Stuck-at Fault Model, Stuck-Open and Stuck-Short faults, Boundary scan check, JTAG technology, TAP controller and TAP controller state diagram, Scan path, Full and Partial scan, BIST.
This book concentrates on common classes of hardware architectures and design problems, and focuses on the process of transitioning design requirements into synthesizable HDL code. Using his extensive, wide-ranging experience in computer architecture and hardware design, as well as in his training and consulting work, Ben provides numerous examples of real-life designs illustrated with VHDL and Verilog code. This code is shown in a way that makes it easy for the reader to gain a greater understanding of the languages and how they compare. All code presented in the book is included on the companion CD, along with other information, such as application notes.
This book addresses a means of quantitatively assessing functional verification progress. Without this process, design and verification engineers, and their management, are left guessing whether or not they have completed verifying the device they are designing. Using the techniques described in this book, they will learn how to build a toolset which allows them to know how close they are to functional closure. This is the first book to introduce a useful taxonomy for coverage of metric classification. Using this taxonomy, the reader will clearly understand the process of creating an effective coverage model. This book offers a thoughtful and comprehensive treatment of its subject for anybody who is really serious about functional verification.
Verilog® Quickstart, Second Edition, has been revised and updated in accordance with the new IEEE 1364-1999 standard, much of which applies to synthesizable Verilog. New examples have been included as well as additional material added throughout. Verilog® Quickstart, Second Edition, focuses on the most commonly used elements of the Verilog Hardware Description Language used by designers for simulation and synthesis of ASICS and FPGAs. This book makes learning Verilog easy by following a well proven approach used in the author's classes for many years. Verilog® Quickstart, Second Edition, is a basic, practical, introductory textbook for professionals and students alike. This book explains how a designer can be more effective through the use of the Verilog Hardware Description Language to simulate and document a design. Verilog® Quickstart, Second Edition, presents some of the formal Verilog syntax and definitions and then shows practical uses. This book does not oversimplify the Verilog language nor does it emphasize theory. Verilog® Quickstart, Second Edition, has over 100 examples that are used to illustrate aspects of the language. The later chapters focus on working with modeling style and explaining why and when one would use different elements of the language. Another feature of the book is the chapter on state machine modeling. There is a chapter on test benches and testing strategy as well as a chapter on debugging. Verilog® Quickstart, Second Edition, is designed to teach the Verilog language, to show the designer how to model in Verilog and to explain the basics of using Verilog simulators. The accompanying disk contains over 100 runable Verilog examples from the book.